1. Field of the Invention
The present invention relates to a semiconductor photoreceptor device and a manufacturing method therefor, and more particularly to a semiconductor photoreceptor device used for optical communications systems, etc. and a manufacturing method therefor.
2. Background Art
The capacity of communications systems has been increased to satisfy the dramatically increasing demand for communications. Accordingly, there has been a need for higher-speed, higher-efficiency yet lower-cost and smaller optical communications devices.
In transmission systems for optical communications, efforts are being made to develop and improve high-speed optical communications devices to accommodate 40-GHz band signal light.
One factor in determining the response speed of semiconductor photoreceptor devices such as PIN photodiodes and avalanche photodiodes is their CR time constant. (The term “photodiode” is hereinafter abbreviated as “PD”.) The CR time constant of a semiconductor photoreceptor device is determined by its device capacitance and device resistance. Therefore, increasing the response speed of the semiconductor photoreceptor device requires reducing the CR time constant. Various techniques have been used to reduce the CR time constant of semiconductor photoreceptor devices for super-high-speed communications (the 40 GHz band or higher).
For example, the diameter of the light receiving portion of semiconductor photoreceptor devices has been reduced to reduce the capacitance. Further, the device capacitance of other portions has also been reduced. One method for reducing the pad capacitance of the electrode pad portion is to deposit a thick insulating film of SiO2 or SiN under it.
To reduce the pad capacitance to negligible levels, one known technique provides a semiconductor photoreceptor device configured such that a waveguide type absorption layer structure is formed on a semi-insulative InP substrate and buried in semi-insulative InP so as to provide a flat surface, allowing the surfaces of the anode and the cathode electrodes to have substantially the same height. This enables the flip-chip mounting of the semiconductor photoreceptor device. See, for example, “40 Gbps Waveguide Photodiode for Flip-Chip Assembly”, Extended Abstracts of The 49th Spring Meeting of The Japan Society of Applied Physics and Related Societies (held at Shonan School of Tokai University in March 2002), p. 1152, 27a-ZG-7.
Another known technique provides a semiconductor photoreceptor device configured such that: it has a buried waveguide type absorption layer structure employing a semi-insulative semiconductor substrate; and Be, Mg, or C is used as a p-type impurity to reduce the diffusion of Zn into the light absorption layer and the blocking layer. See, for example, Japanese Laid-Open Patent Publication No. 2004-146408 (paragraph [0006] and FIGS. 1 to 3).
Still another known technique provides a configuration in which: a semiconductor photoreceptor device is formed on a semi-insulative InP substrate; the n-type electrode is formed on the back side of the semi-insulative InP substrate; the p-side bonding pad is formed on the semi-insulative InP substrate with a silicon nitride antireflective film in between; and the wiring from the p-side electrode to the p-side bonding pad is formed on an n-type layer with the silicon nitride antireflective film in between. See, for example, Japanese Patent Laid-Open No. 2004-152942 (paragraphs [0028] to [0034] and FIGS. 1, 4, and 5).
Yet another known technique provides a configuration in which: a semi-insulative substrate is formed to have a protrusion; a photoreceptor device is formed around or adjacent the protrusion; and the electrode pad connected to the p-electrode of the photoreceptor device is formed on the protrusion, which is located at substantially the same height as the p-electrode. See, for example, Japanese Laid-Open Patent Publication No. 2004-165529 (paragraphs [0063] to [0068] and FIGS. 7 and 6).
Still a further known technique etches an InP substrate laminated over a semi-insulative InP substrate whose principal surface is a (100) plane by use of HBr solution so as to produce a (111)A plane. See, for example, Japanese Patent Laid-Open No. 2002-217446 (paragraphs [0015] to [0019] and FIG. 7).
As described above, a conventional semiconductor photoreceptor device is configured such that a waveguide type absorption layer structure is formed on a semi-insulative InP substrate and buried in semi-insulative InP, which enables the flip-chip mounting of the semiconductor photoreceptor device and thereby reduces the pad capacitance. However, since the semi-insulative InP burying layer is formed on the semi-insulative InP substrate using a regrowth technique, a silicon layer may be undesirably formed at the regrowth interface between the semi-insulative InP substrate and the semi-insulative burying layer depending on the material and the regrowth conditions. (This lamination layer is hereinafter referred to as an Si pile-up layer.)
For example, SIMS analysis was conducted on the growth interface between a semi-insulative Fe-doped InP substrate and an Fe-doped InP layer grown on the substrate. (“Fe-doped InP” is hereinafter abbreviated to as “Fe—InP”.) The amount of Si detected in an interface portion approximately 0.5 μm thick was 1×1018 atoms/cc (peak value).
This approximately 0.5 μm thick layer is considered to be an Si pile-up layer. Since this Si pile-up layer is connected with the n-type layer of the semiconductor photoreceptor device, it becomes a conductive layer, forming pad capacitance (a capacitance due to a pad) between the Si pile-up layer and the electrode pad portion for the p-electrode and the lead-out electrode portion for connecting the electrode pad portion and the p-electrode.
It has been found that if such a pad capacitance is present, the high-frequency response of the semiconductor photoreceptor device degrades more severely with increasing electrode pad area. Furthermore, the response of the semiconductor photoreceptor device also degrades at low frequencies around 10 GHz.
The pad capacitance due to the Si pile-up layer does not affect signal light having relatively low frequencies (up to 40 GHz) very much. With signal light having frequencies higher than 40 GHz, however, the response degrades 1 dB at frequencies in the neighborhood of 10 GHz. Such degradation of the response in this frequency region may lead to an unfavorable eye pattern. (The eye pattern can be used as an indicator when evaluating the high frequency characteristics of a semiconductor photoreceptor device.)
Thus, the pad capacitance degrades the high frequency characteristics of the semiconductor photoreceptor device and thereby prevents a favorable eye pattern from being formed, resulting in a reduction in the yield of the semiconductor photoreceptor device.
To prevent degradation of the high frequency characteristics due to the Si pile-up layer, a groove reaching the Fe—InP substrate may be formed under the lead-out electrode portion such that the lead-out electrode portion connects between the p-electrode and the electrode pad portion in an air bridging manner, thereby reducing the pad capacitance.
This configuration, however, requires a complicated manufacturing process since the lead-out electrode portion must be suspended in air, making it difficult to produce the semiconductor photoreceptor device. Furthermore, this configuration suffers from lack of reliability since the air-bridge-like lead-out electrode portion might break.